Advancement in semiconductor technologies allows implementation of multiple memories on a single chip. Due to their high density, memories are prone to faults which reduce the total chip yield. In order to correct such defects memory sub-systems are provided with a repair mechanism that makes use of redundant memory locations.
A memory is periodically tested by an external test hardware or by an on chip dedicated hardware (i.e. memory Built-In-Self-Test (BIST)) in order to identify fault locations. A BIST mechanism uses a built-in algorithm which performs a series of read-write operations to identify one or more defective row or column addresses. The defective row/column is then replaced by a redundant row/column depending upon whether there is a row or column redundancy support. At the end of the test process repair data of the repairable memories is programmed onto the fuse macro cells provided on the chip for all small/medium memories during wafer production. This fused information is further used during chip functional operation as a repair solution.
U.S. Patent Publication No. 2008/0065929A1 entitled “Method and Apparatus for storing and distributing memory repair information” to Nadeau-Dostie, et al. published on Mar. 13, 2008 discloses a system for repairing embedded memories on an integrated circuit. The system comprises an external Built-In Self-repair Register (BISR) associated with every reparable memory on the circuit. Each BISR is configured to accept a serial input from a daisy chain connection and to generate a serial output to a daisy chain connection, so that a plurality of BISRs are connected in a daisy chain with a fuse box controller. The fuse box controller has no information as to the number, configuration or size of the embedded memories, but determines, upon power up, the length of the daisy chain. With this information, the fuse box controller may perform a corresponding number of serial shift operations to move repair data to and from the BISRs and into and out of a fuse box associated with the controller. Memories having a parallel repair interface are supported by a parallel address bus and enable control signal on the BISR, while those having a serial repair interface are supported by a parallel daisy chain path that may be selectively cycled to shift the contents of the BISR to an internal serial register in the memory. Preferably, each of the BISRs has an associated repair analysis facility having a parallel address bus and enable control signal by which fuse data may be dumped in parallel into the BISR and from there, either uploaded to the fuse box through the controller or downloaded into the memory to effect repairs. Advantageously, pre-designed circuit blocks may provide daisy chain inputs and access ports to affect the inventive system there along or to permit the circuit block to be bypassed for testing purposes. While U.S. Patent Publication No. 2008/0065929A1 provides a fuse box module to repair memory structures present in a single power domain, it remains specific to the number, size and configuration of the embedded memory locations and is incapable of supporting memories spanning across plurality of power domains.